AVAILABLE FOR PURCHASE: ADVANCED PACKAGING PRODUCTION FACILITY, JAPAN
ATREG has been retained to facilitate the sale of an operational back-end facility located in Japan that specializes in the development, design, assembly, and testing of advanced semiconductor packages, including MCP (Multi-Chip) and SiP (System in Package) among other advanced packaging technologies.
HIGHLIGHTS
- Ability to produce smaller, thinner, high-quality, multiple-stacked products capable of meeting customer demand in the mobile communications market
- Potential multi-year supply contract from the seller during the buyer’s product qualification and production ramp
- Experienced senior management team and highly motivated and experienced workforce to enable new package and test design, technology innovation, and implementation
- Stable region with a mature semiconductor ecosystem, reputation for high-quality manufacturing, and secure intellectual property (IP) environment
- Established supply chain with long-standing relationships with local packaging material suppliers
Please call Nick Papa at ATREG at +1.206.268.7804 or email him for more detailed information on this offering.
EXECUTIVE Q&A: E. JAN VARDAMAN, PRESIDENT & FOUNDER, TECHSEARCH INTERNATIONAL
With headquarters in Austin, TX, TechSearch International, Inc. is a leading consulting company in the field of advanced semiconductor packaging technology. ATREG recently sat down with E. Jan Vardaman, the company’s President & Founder, to discuss the latest trends in the back-end sector, including technology advancements, competition, and consolidation.
The outsourced semiconductor packaging and test (OSAT) market is very competitive and revenue growth is slowing. As competition intensifies and capital requirements increase, what can we expect to see in the OSAT market?
We should expect to see continued consolidation. The increased level of investment requires revenue growth that can support the continued development of advanced packages.
With wafer-based packaging processes going mainstream, chip manufacturing can no longer be neatly divided between front-end and back-end. TSMC is already offering fan-out packaging and Samsung may follow suit. Can we expect to see more foundries such as GLOBALFOUNDRIES and UMC offering advanced packaging services?
Each foundry has a different strategy. The main revenue source for the foundry is providing the customer with wafers specific to their design. Filling the fab generates the revenue for the foundry. In the case of TSMC, they were able to obtain 100% of Apple’s application processor foundry business by offering a co-designed package (InFO) that provided better electrical and thermal performance than other package choices. Other foundries are working with a different model in which they work with OSATs to select the package required to meet the customer’s need. Few foundries, other than Intel, have assembly operations internal to their business.
Like the rest of the semiconductor industry, we’ve seen a lot of horizontal consolidation among OSAT companies (ASE/SPIL, Amkor/J-Devices, JCET/STATS). In the future, can you envision greater vertical integration between OSATs and downstream EMS companies?
We see OSATs and EMS companies competing for the same business in the system-in-package (SiP) space. In some cases, such as ASE’s purchase of USI, acquisitions have occurred. We see this as the exception in the short term. EMS companies have added capabilities to do module assembly and this trend will continue.
Do you expect more competition between OSATs and EMS companies in the SiP space?
SiP is defined as two or more dissimilar die, typically combined with other components such as passives, filters, MEMS, sensors, and antennas, assembled into a standard footprint package to create a functional system or subsystem. Traditionally, there has been separation between first level (semiconductor packaging) and second level (board assembly). OSATs dealt directly with the IDM or foundry to design and deliver packaged semiconductors while the EMS companies partnered with the OEMs to design and assemble cards and boards. In the new SiP business model, the distinctions are blurring. SiP represents a large potential market for both types of companies. Manufacturing of SiPs requires a combination of skills. The ability to procure bare die to a reasonable quality level and to handle the die without damage are two very critical factors. OSAT companies have strong capabilities in this area, especially when it comes to design complex SiPs and test them. Surface-mount component (SMT) capability is typically found at EMS companies. Because of historically low margins, EMS companies have developed systems to purchase materials and components at the lowest-possible cost.
What is the impact of the trend in fan-out WLP (FO-WLP) adoption?
FO-WLP is a disruptive technology. In the case of the application processor, it represents a move from a flip chip CSP to a package where the redistribution layer (RDL) is used for the interconnect layer instead of a laminate substrate. As the adoption rate increases, the demand for laminate substrates declines. There are additional devices that are using FO-WLP with a variety of processes. In many cases, such as power management integrated circuits (PMICs), RF ICs, and audio CODECs, the packages are migrating from fan-in WLP to FO-WLP.
About E. Jan Vardaman
E. Jan Vardaman is President and Founder of Austin, TX-based TechSearch International, Inc. which has provided market research and technology trend analysis in semiconductor packaging since 1987. She is the co-author of How to Make IC Packages (by Nikkan Kogyo Shinbunsha), a columnist with Printed Circuit Design & Fab/Circuits Assembly, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. Jan is a senior member of IEEE CPMT and an IEEE CPMT Distinguished Lecturer. She served two terms as part of the IEEE CPMT Board of Governors and is a member of SEMI, MEPTEC, and IMAPS. Before founding TechSearch International, Jan served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.
CONNECT WITH US AT INDUSTRY EVENTS THIS FALL!
Did you know that ATREG’s combined years of experience facilitating complex semiconductor transactions all over the world can help your company minimize time to market and maximize your final ROI? Our transactions encompass semiconductor fabs, cleanrooms, and technology campuses, including land, buildings, intellectual property (IP), complete tool lines, and business unit elements (supply contracts, workforce, etc.) If your company is planning to dispose of or acquire any advanced technology manufacturing asset in the near future, we’d love to talk! Please email us to set up an appointment with one of our advisors at any of the following industry events to discuss your specific requirements:
- GSA U.S. Executive Forum, October 6, Menlo Park, USA
- SEMICON Europa, October 25-27, Grenoble, France
- GSA Annual Awards Dinner, December 8, Santa Clara, USA
- SEMICON Japan, December 14-16, Tokyo, Japan
We look forward to seeing you there!